WEKO3
アイテム
{"_buckets": {"deposit": "3f016185-27e9-44eb-a451-10f86253b392"}, "_deposit": {"created_by": 2, "id": "12512", "owners": [2], "pid": {"revision_id": 0, "type": "depid", "value": "12512"}, "status": "published"}, "_oai": {"id": "oai:nagasaki-u.repo.nii.ac.jp:00012512", "sets": ["65"]}, "author_link": ["46450", "46452", "46451", "46453"], "item_9_biblio_info_6": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2011-09", "bibliographicIssueDateType": "Issued"}, "bibliographicPageEnd": "481", "bibliographicPageStart": "478", "bibliographic_titles": [{"bibliographic_title": "2011 21st International Conference on Field Programmable Logic and Applications"}]}]}, "item_9_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7∼9% of available slices of a Virtex-5 FPGA.", "subitem_description_type": "Abstract"}]}, "item_9_description_5": {"attribute_name": "内容記述", "attribute_value_mlt": [{"subitem_description": "2011 International Conference on Field Programmable Logic and Applications (FPL) : Chania, Greece, 2011.09.5-2011.09.7", "subitem_description_type": "Other"}]}, "item_9_description_63": {"attribute_name": "引用", "attribute_value_mlt": [{"subitem_description": "FPL 2011, pp.478-481", "subitem_description_type": "Other"}]}, "item_9_publisher_33": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_9_relation_12": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1109/FPL.2011.94", "subitem_relation_type_select": "DOI"}}]}, "item_9_relation_9": {"attribute_name": "ISBN", "attribute_value_mlt": [{"subitem_relation_type_id": {"subitem_relation_type_id_text": "978-1-4577-1484-9", "subitem_relation_type_select": "ISBN"}}]}, "item_9_rights_13": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "© 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]}, "item_9_version_type_16": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_ab4af688f83e57aa", "subitem_version_type": "AM"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Dohi, Keisuke"}], "nameIdentifiers": [{"nameIdentifier": "46450", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yorita, Yuji"}], "nameIdentifiers": [{"nameIdentifier": "46451", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Shibata, Yuichiro"}], "nameIdentifiers": [{"nameIdentifier": "46452", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Oguri, Kiyoshi"}], "nameIdentifiers": [{"nameIdentifier": "46453", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2020-12-22"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "FPL2011_478.pdf", "filesize": [{"value": "356.2 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 356200.0, "url": {"label": "FPL2011_478.pdf", "url": "https://nagasaki-u.repo.nii.ac.jp/record/12512/files/FPL2011_478.pdf"}, "version_id": "0b422fff-7a61-4a66-987f-05e884cd3c48"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "conference paper", "resourceuri": "http://purl.org/coar/resource_type/c_5794"}]}, "item_title": "Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation"}]}, "item_type_id": "9", "owner": "2", "path": ["65"], "permalink_uri": "http://hdl.handle.net/10069/26676", "pubdate": {"attribute_name": "公開日", "attribute_value": "2011-12-06"}, "publish_date": "2011-12-06", "publish_status": "0", "recid": "12512", "relation": {}, "relation_version_is_last": true, "title": ["Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation"], "weko_shared_id": -1}
Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation
http://hdl.handle.net/10069/26676
http://hdl.handle.net/10069/26676d727c41f-e13f-495a-afd8-aa133b56c2c5
名前 / ファイル | ライセンス | アクション |
---|---|---|
FPL2011_478.pdf (356.2 kB)
|
|
Item type | 会議発表論文 / Conference Paper(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2011-12-06 | |||||
タイトル | ||||||
タイトル | Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Dohi, Keisuke
× Dohi, Keisuke× Yorita, Yuji× Shibata, Yuichiro× Oguri, Kiyoshi |
|||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7∼9% of available slices of a Virtex-5 FPGA. | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 2011 International Conference on Field Programmable Logic and Applications (FPL) : Chania, Greece, 2011.09.5-2011.09.7 | |||||
書誌情報 |
2011 21st International Conference on Field Programmable Logic and Applications p. 478-481, 発行日 2011-09 |
|||||
ISBN | ||||||
識別子タイプ | ISBN | |||||
関連識別子 | 978-1-4577-1484-9 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/FPL.2011.94 | |||||
権利 | ||||||
権利情報 | © 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | IEEE | |||||
引用 | ||||||
内容記述タイプ | Other | |||||
内容記述 | FPL 2011, pp.478-481 |