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A COMBINING TECHNIQUE OF RATE LAW FUNCTIONS FOR A COST-EFFECTIVE RECONFIGURABLE BIOLOGICAL SIMULATOR
http://hdl.handle.net/10069/19231
http://hdl.handle.net/10069/19231a354c927-32a5-48a0-80aa-d95422922730
名前 / ファイル | ライセンス | アクション |
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ICFPLA2007_808.pdf (203 KB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2008-09-02 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | A COMBINING TECHNIQUE OF RATE LAW FUNCTIONS FOR A COST-EFFECTIVE RECONFIGURABLE BIOLOGICAL SIMULATOR | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Yamada, Hideki
× Yamada, Hideki× Shibata, Yuichiro× Osana, Yasunori× Yoshimi, Masato× Iwaoka, Yow× Nishikawa, Yuri× Kojima, Toshinori× Amano, Hideharu× Funahashi, Akira× Hiroi, Noriko× Kitano, Hiroaki× Iwanaga, Naoki× Oguri, Kiyoshi |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In order to simulate large scale biological models with a reconfigurable FPGA-based biochemical simulator system, reduction of required resources are essential. This paper proposes a method which combines common terms in rate law functions appeared in biochemical models and generates a shared hardware module used for numerical integration. In this approach, two functions are combined in a tree structure level, followed by pipeline scheduling and arithmetic module binding. The evaluation result reveals that this approach reduces hardware resources by 31.4 % on average at the cost of 14.4 % throughput degradation. |
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内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 2007 International Conference on Field Programmable Logic and Applications : Amsterdam, Netherlands, 2007.08.27-2007.08.29 | |||||
書誌情報 |
Proceedings 2007 International Conference on Field Programmable Logic and Applications FPL p. 808-811, 発行日 2007-08 |
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DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/FPL.2007.4380774 | |||||
権利 | ||||||
権利情報 | (c)2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
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フォーマット | ||||||
内容記述タイプ | Other | |||||
内容記述 | application/pdf | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers | |||||
引用 | ||||||
内容記述タイプ | Other | |||||
内容記述 | International Conference on Field Programmable Logic and Applications 2007, pp.808-811 |