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Deep-pipelined FPGA implementation of ellipse estimation for eye tracking
http://hdl.handle.net/10069/31155
http://hdl.handle.net/10069/3115536e44ea6-30ec-4e26-a5f5-e55393d46a6a
名前 / ファイル | ライセンス | アクション |
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FPL2012_458.pdf (958.9 kB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2013-04-01 | |||||
タイトル | ||||||
タイトル | Deep-pipelined FPGA implementation of ellipse estimation for eye tracking | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | External memory | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Eye-tracking | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | FPGA implementations | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Gauss-Jordan elimination | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Lu decomposition | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Optimal algorithm | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | RANSAC algorithm | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Resource usage | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Starbursts | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Energy utilization | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Field programmable gate arrays (FPGA) | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Algorithms | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Dohi, Keisuke
× Dohi, Keisuke× Hatanaka, Yuma× Negi, Kazuhiro× Shibata, Yuichiro× Oguri, Kiyoshi |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | This paper presents a deep-pipelined FPGA implementation of real-time ellipse estimation for eye tracking. The system is constructed by the Starburst algorithm on a stream-oriented architecture and the RANSAC algorithm without any external memories. In particular, the paper presents comparative results between three different hypothesis generators for the RANSAC algorithm based on Cramer's rule, Gauss-Jordan elimination and LU decomposition. Comparison criteria include resource usage, throughput and energy consumption. The result shows that the three implementations have different characteristics and the optimal algorithm needs to be chosen depending on the amount of resources on FPGAs and required performance. | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 22nd International Conference on Field Programmable Logic and Applications, FPL 2012;Oslo;29 August 2012through31 August 2012 | |||||
書誌情報 |
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on p. 458-463, 発行日 2012 |
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DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/FPL.2012.6339144 | |||||
権利 | ||||||
権利情報 | © 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | |||||
著者版フラグ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
出版者 | ||||||
出版者 | IEEE | |||||
引用 | ||||||
内容記述タイプ | Other | |||||
内容記述 | Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on, pp.458-463; 2012 |