@inproceedings{oai:nagasaki-u.repo.nii.ac.jp:00005877,
 author = {Iwasaki, Aiko and Dohi, Keisuke and Shibata, Yuichiro and Oguri, Kiyoshi and Harasawa, Ryuichi},
 book = {Field Programmable Logic and Applications (FPL), 2014 24th International Conference on},
 month = {Oct},
 note = {This paper presents implementation and evaluation of an accelerator architecture for soft-cores to speed up reduction process for the arithmetic on GF(2m) used in Elliptic Curve Cryptography (ECC) systems. In this architecture, the word size of the accelerator can be customized when the architecture is configured on an FPGA. Focusing on the fact that the number of the reduction processing operations on GF(2m) is affected by the irreducible polynomial and the word size, we propose to employ an unconventional word size for the accelerator depending on a given irreducible polynomial and implement a MIPS-based soft-core processor coupled with a variable-word size accelerator. As a result of evaluation with several polynomials, it was shown that the performance improvement of up to 10.2 times was obtained compared to the 32-bit word size, even taking into account the maximum frequency degradation of 20.4% caused by changing the word size. The advantage of using unconventional word sizes was also shown, suggesting the promise of this approach for low-power ECC systems., 24th International Conference on Field Programmable Logic and Applications, FPL 2014; Technische Universitat MunchenMunich; Germany; 1 September 2014 through 5 September 2014, Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, 6927388; 2014},
 pages = {1--4},
 publisher = {IEEE},
 title = {A soft-core processor for finite field arithmetic with a variable word size accelerator},
 year = {2014}
}