{"created":"2023-05-15T16:36:16.781637+00:00","id":9292,"links":{},"metadata":{"_buckets":{"deposit":"bf2d486d-7cde-46be-8019-44a74b01bf80"},"_deposit":{"created_by":2,"id":"9292","owners":[2],"pid":{"revision_id":0,"type":"depid","value":"9292"},"status":"published"},"_oai":{"id":"oai:nagasaki-u.repo.nii.ac.jp:00009292","sets":["14:65"]},"author_link":["37320","37318","37319","37321"],"item_9_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-12","bibliographicIssueDateType":"Issued"},"bibliographicPageStart":"6132679","bibliographic_titles":[{"bibliographic_title":"2011 International Conference on Field-Programmable Technology, FPT 2011"}]}]},"item_9_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves 62.5 fps of the detection throughput, showing 96.6% and 20.7% of the detection rate and the false positive rate, respectively. Moreover, if a highspeed camera device is available, the maximum throughput of 112 fps is expected to be accomplished, which is 7.5 times faster than software implementation.","subitem_description_type":"Abstract"}]},"item_9_description_63":{"attribute_name":"引用","attribute_value_mlt":[{"subitem_description":"2011 International Conference on Field-Programmable Technology, FPT 2011, Article number6132679; 2011","subitem_description_type":"Other"}]},"item_9_publisher_33":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_9_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1109/FPT.2011.6132679","subitem_relation_type_select":"DOI"}}]},"item_9_rights_13":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."}]},"item_9_version_type_16":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_ab4af688f83e57aa","subitem_version_type":"AM"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Negi, Kazuhiro"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Dohi, Keisuke"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shibata, Yuichiro"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Oguri, Kiyoshi"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-12-22"}],"displaytype":"detail","filename":"FPT2011_6132679.pdf","filesize":[{"value":"1.9 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"FPT2011_6132679.pdf","url":"https://nagasaki-u.repo.nii.ac.jp/record/9292/files/FPT2011_6132679.pdf"},"version_id":"9280ca77-f253-45ca-aba5-76a9f7ff3dfe"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Detection rates","subitem_subject_scheme":"Other"},{"subitem_subject":"Empirical evaluations","subitem_subject_scheme":"Other"},{"subitem_subject":"External memory","subitem_subject_scheme":"Other"},{"subitem_subject":"False positive rates","subitem_subject_scheme":"Other"},{"subitem_subject":"FPGA implementations","subitem_subject_scheme":"Other"},{"subitem_subject":"Human detection","subitem_subject_scheme":"Other"},{"subitem_subject":"Image-based","subitem_subject_scheme":"Other"},{"subitem_subject":"Maximum through-put","subitem_subject_scheme":"Other"},{"subitem_subject":"Off-line training","subitem_subject_scheme":"Other"},{"subitem_subject":"Software implementation","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm"}]},"item_type_id":"9","owner":"2","path":["65"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-11-29"},"publish_date":"2012-11-29","publish_status":"0","recid":"9292","relation_version_is_last":true,"title":["Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm"],"weko_creator_id":"2","weko_shared_id":-1},"updated":"2023-05-16T01:49:28.180174+00:00"}