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Optimal bus capacitance design for system stability in on-board distributed power architecture
http://hdl.handle.net/10069/20829
http://hdl.handle.net/10069/2082962b41f82-6c53-4214-b963-149e47c7ae8b
名前 / ファイル | ライセンス | アクション |
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EPE-PEMC2008_393.pdf (284.6 kB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2008-12-17 | |||||
タイトル | ||||||
タイトル | Optimal bus capacitance design for system stability in on-board distributed power architecture | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Abe, Seiya
× Abe, Seiya× Hirokawa, Masahiko× Shoyama, Masahito× Ninomiya, Tamotsu |
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抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | Recently, the distributed power system is mainly used for the power supply system which requires the low-voltage / high-current output. The distributed power system consists of bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of bus converter and input impedance of POL causes system instability, and it has been an actual problem. Increasing the bus capacitor, system stability can be reduced easily. However, due to the limited space on the system board, increasing of bus capacitors is impractical. The urgent solution of the issue is desired strongly. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed, and it is conformed by experimentally for stability criterion. Furthermore, the optimal intermediate bus capacitance design for system stability is proposed. | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 2008 13th International Power Electronics and Motion Control Conference, EPE-PEMC 2008; Poznan; 1 September 2008 through 3 September 2008 | |||||
書誌情報 |
2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) p. 393-399, 発行日 2008-09 |
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ISBN | ||||||
識別子タイプ | ISBN | |||||
関連識別子 | 978-1-4244-1741-4 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/EPEPEMC.2008.4635297 | |||||
権利 | ||||||
権利情報 | (c)2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronics Engineers | |||||
引用 | ||||||
内容記述タイプ | Other | |||||
内容記述 | EPE-PEMC 2008, pp.393-399 |