{"_buckets": {"deposit": "e419fdc1-53a6-4e89-85b3-a3f78ca04945"}, "_deposit": {"created_by": 6, "id": "2000615", "owner": "6", "owners": [6], "pid": {"revision_id": 0, "type": "depid", "value": "2000615"}, "status": "published"}, "_oai": {"id": "oai:nagasaki-u.repo.nii.ac.jp:02000615", "sets": ["21"]}, "author_link": [], "item_2_biblio_info_6": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2024-03-01", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "3", "bibliographicPageEnd": "539", "bibliographicPageStart": "531", "bibliographicVolumeNumber": "E107.A", "bibliographic_titles": [{"bibliographic_title": "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences", "bibliographic_titleLang": "en"}]}]}, "item_2_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "This paper presents an FPGA implementation of real-time high dynamic range (HDR) synthesis, which expresses a wide dynamic range by combining multiple images with different exposures using image pyramids. We have implemented a pipeline that performs streaming processing on images without using external memory. However, implementation for high-resolution images has been difficult due to large memory usage for line buffers. Therefore, we propose an image compression algorithm based on adaptive differential pulse code modulation (ADPCM). Compression modules based on the algorithm can be easily integrated into the pipeline. When the image resolution is 4K and the pyramid depth is 7, memory usage can be halved from 168.48 % to 84.32 % by introducing the compression modules, resulting in better quality.", "subitem_description_language": "en", "subitem_description_type": "Abstract"}]}, "item_2_description_63": {"attribute_name": "引用", "attribute_value_mlt": [{"subitem_description": "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E107.A (3), pp. 531-539", "subitem_description_language": "en", "subitem_description_type": "Other"}]}, "item_2_publisher_33": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "Institute of Electronics Information Communication Engineers", "subitem_publisher_language": "en"}]}, "item_2_relation_12": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1587/transfun.2023VLP0017", "subitem_relation_type_select": "DOI"}}]}, "item_2_rights_13": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "© 2024 The Institute of Electronics, Information and Communication Engineers.", "subitem_rights_language": "en"}]}, "item_2_source_id_7": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "0916-8508", "subitem_source_identifier_type": "ISSN"}]}, "item_2_text_62": {"attribute_name": "出版者別言語", "attribute_value_mlt": [{"subitem_text_language": "ja", "subitem_text_value": "一般社団法人 電子情報通信学会"}]}, "item_2_version_type_16": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "NISHIMURA, Masahiro", "creatorNameLang": "en"}]}, {"creatorNames": [{"creatorName": "MANABE, Taito", "creatorNameLang": "en"}]}, {"creatorNames": [{"creatorName": "SHIBATA, Yuichiro", "creatorNameLang": "en"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_access", "date": [{"dateType": "Available", "dateValue": "2024-03-19"}], "download_preview_message": "", "file_order": 0, "filename": "IEICETFECCSE107.A_531.pdf", "filesize": [{"value": "11.5 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "mimetype": "application/pdf", "size": 11500000.0, "url": {"url": "https://nagasaki-u.repo.nii.ac.jp/record/2000615/files/IEICETFECCSE107.A_531.pdf"}, "version_id": "c9237bcb-a14f-46f6-a394-2b251c433fc9"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "FPGA", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}, {"subitem_subject": "HDR synthesis", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}, {"subitem_subject": "image compression", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Pipelined ADPCM Compression for HDR Synthesis on an FPGA", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Pipelined ADPCM Compression for HDR Synthesis on an FPGA", "subitem_title_language": "en"}]}, "item_type_id": "2", "owner": "6", "path": ["21"], "permalink_uri": "http://hdl.handle.net/10069/0002000615", "pubdate": {"attribute_name": "PubDate", "attribute_value": "2024-03-19"}, "publish_date": "2024-03-19", "publish_status": "0", "recid": "2000615", "relation": {}, "relation_version_is_last": true, "title": ["Pipelined ADPCM Compression for HDR Synthesis on an FPGA"], "weko_shared_id": -1}
Pipelined ADPCM Compression for HDR Synthesis on an FPGA
http://hdl.handle.net/10069/0002000615
http://hdl.handle.net/10069/0002000615